Informador Técnico
ISSN: 2256-5035 (Electrónico)
ISSN: 0122-056X (Impreso)
Formato: Electrónico / Acceso Abierto
Frecuencia: Números Semestrales
Revisión por Pares: Doble Ciego
ADVANCED ENCRYPTION STANDARD. [On-line] Avalaible at http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
AL-SHAIKHLI, I. F, ALAHMAD, M. A., MUNTHIR, K. Hash Function of Finalist SHA-3: Analysis Study. In: International Journal of Advanced Computer Science and Information Technology (IJACSIT) Vol. 2, No. 2 (Apr., 2013) pp. 1-12, ISSN: 2296-1739.
AUMASSON, J. P., FISCHER, S., KHAZAEI, S., MEIER, W., and RECHBERGER, C. New features of Latin dances: analysis of Salsa, ChaCha and Rumba. In: FSE (2008).
AUMASSON, J.P., HENZEN, L., MEIER, W. and PHAN, R. C. SHA-3 proposal BLAKE, 2011.
BALDWIN, B.Baldwin B., Hanley N., Hamilton M., Lu L., Byrne A., O’Neill M. and Marnane W. P.. FPGA Implementations of the Round Two SHA-3 Candidates. In: The Second SHA-3 Candidate Conference (Aug., 2010).
BERTONI, G., DAEMEN, J., PEETERS, M., VAN ASSCHE, G. and VAN KEER, R. Cryptographic sponge functions. [On-line] Available at http://sponge.noekeon.org/ [Citado en enero, 2011].
BERTONI, G., DAEMEN, J., PEETERS, M., VAN ASSCHE, G. and VAN KEER, R. Keccak implementation overview. [On-line] Avalaible at http://keccak.noekeon.org/Keccak-implementation-3.2.pdf
FERGUSON, N. et al. The Skein Hash Function Family, 2011.
GAJ, K., HOMSIRIKAM, E. and ROGAWSKI, M. Comprehensive Comparison of Hardware Performance of Fourteen Round 2 SHA-3 Candidates with 512-bit Outputs Using Field Programmable Gate Arrays. In: The Second SHA-3 Candidate Conference (Aug., 2010).
GAURAVARAM, P. et al. Grostl-a SHA-3 candidate, 2011.
GUO, X., HUANG, S., NAZHANDALI, L. and SCHAUMONT, P. Fair and Comprehensive Performance Evaluation of 14 Second Round SHA-3 ASIC Implementations. In: The Second SHA-3 Candidate Conference (August 2010).
GUO, X. et al. Silicon Implementation of SHA-3 Finalists: Blake, Grostl, JH, Keccak and Skein. Center for Embedded Systems for Critical Applications (CESCA), Virginia Tech, 2011.
HENZEN, Luca, et al. Developing a hardware evaluation method for sha-3 candidates. In: Mangard and Standaert [21], pp.248-263.
HOMSIRIKAMOL, E., ROGAWSKI, M. and GAJ, K. Comparing Hardware Performance of Round 3 SHA-3 Candidates using Multiple Hardware Architectures in Xilinx and Altera FPGA.
George Mason University, 2011. HOMSIRIKAMOL, E. Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGA. George Mason University, 2011.
HONGJUN, W. The Hash Function JH. Singapore, Institute for Infocomm Research y Nanyang Technological University, 2011.
KNOPF, C. Cryptographic Hash Functions. Leibniz Universität Hannover, in section 3.4 - The Compression Function (Nov., 2007).
NAMIN, A. H. and HASAN, M. A. Hardware Implementation of the Compression Function for Selected SHA-3 Candidates. Department of Electrical and Computer Engineering, University of Waterloo, Canada, 2011.
NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY. Announcing the Secure Hash Standard. In: Federal Information Processing Standards Publication 180-3 (Oct., 2008). [On-line] Avalaible at http://csrc.nist.gov/publications/PubsFIPS.html#fips180-4
TILLICH, S. et al. Uniform Evaluation of Hardware Implementations of the Round-Two SHA-3 Candidates. In: The Second SHA-3 Candidate Conference (Aug., 2010).